Field of the Invention
The present invention relates to synchronous reset set flip-flop circuits (referred to as RST flip-flop circuits hereinafter), and more particularly to RST flip-flop circuits composed of complementary metal oxide (CMOS) transistors.
2. Description of the Prior Art
Flip-flops perform the memory and counting operation, and are used for counters, memories, shift registers and the like. Among them, as RS flip-flop circuit is the most fundamental flip-flop circuit, and involves positive feedback closed loops with two stages of inverters. The coupling between the inverters is dc coupling for all cases, and the circuit has a feature in that it always stays at a direct-current-wise stable point for the circuit as a whole.
However, the simultaneous input of a set signal and a reset signal is inhibited because it makes the output unstable. In view of this, there was proposed an RST flip-flop circuit which validates a set signal (S) or a reset signal (R) in response to a synchronization signal (T) in order to realize a stable operation of the circuit even if a set signal and a reset signal are simultaneously input transitionally.
Now, a CMOS is composed of P-channel and N-channel MOS transistors and has been known as a circuit element effective for reducing the power consumption. It is possible to construct an RST flip-flop circuit using a CMOS.
In a conventional RST flip-flop circuit as described above, there are provided on the set side and on the reset side two stages of inverter obtained by directly coupling a first transistor and a second transistor with N-channel MOS FETs that are connected in series between an output terminal and the grounding, and a third transistor and a fourth transistor with P-channel MOS FETs that are connected in parallel between a power supply and the output terminal.
The first transistor and the third transistor of the first stage receive a set or a reset signal and the second and the fourth transistor of the first stage receive a synchronizing signal, the first transistor and the third transistor of the second stage receive the output signal of the first stage and the second transistor and the fourth transistor of the second state respectively receive the outputs of the second stage of the opposite side, that is, the output of the second stage on the reset side for the transistor on the set side and that on the set side for the transistor on the reset side. The output signal of the second stage on the set side is the output signal of the circuit as a whole, and the output signal of the second stage on the reset side is the inverted output signal of the circuit as a whole.
With the above-mentioned constitution, when the synchronizing signal goes to "1", the second transistor of the first stage is turned on and the fourth transistor is turned off. Then, the first transistor and the third transistor on the side where either of the set signal and the reset signal went to "1" are turned on and turned off, respectively. When the synchronizing signal is "0", the second transistor is turned off and the fourth transistor is turned on.
Accordingly, in either case a state cannot occur wherein the first transistor and the second transistor are turned on, and either of the third transistor or the fourth transistor is turned on, so that there should not be a current that flows from the power supply to the ground.
On the other hand, there are cases where a "1" signal is not on a sufficiently high level as a set signal or a reset signal, as, for example, in the case where a signal on the read digit line of a semiconductor memory is used. Such a situation arises when an enhancement MOS is used as a transfer gate of the memory cell. In such an example of usage, the third transistor which should be off when the input is "1" will not be turned off completely, so that a leakage current of several microamperes will flow from the power supply to the ground. As a result, the special feature of a CMOS that the standby current is substantially equal to zero cannot be exhibited.